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CAT25010, CAT25020, CAT25040
1K/2K/4K SPI Serial CMOS EEPROM FEATURES
I 10 MHz SPI compatible I 1.8 to 5.5 volt operation I SPI modes (00 & 11) I 16-byte page write buffer I Self-timed write cycle I Hardware and software protection I Block write protection
DESCRIPTION
The CAT25010/20/40 is a 1K/2K/4K Bit SPI Serial CMOS EEPROM internally organized as 128x8/256x8/ 512x8 bits. Catalyst's advanced CMOS Technology substantially reduces device power requirements. The CAT25010/20/40 features a 16-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25010/ 20/40 is designed with software and hardware write protection features including Block Write protection.
- Protect 1/4, 1/2 or all of EEPROM array
I Low power CMOS technology I 1,000,000 program/erase cycles I 100 year data retention I Industrial temperature range I RoHS-compliant 8-lead PDIP, SOIC, TSSOP
and 8-pad TDFN packages. For Ordering Information details, see page 17.
PIN CONFIGURATION
PDIP (L) SOIC (V) TSSOP (Y) TDFN (VP2)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
FUNCTIONAL SYMBOL
VCC
SI CS WP HOLD SCK CAT25010 CAT25020 CAT25040
SO
PIN FUNCTIONS Pin Name
SO SCK WP VCC VSS CS SI HOLD
Function
Serial Data Output Serial Clock Write Protect +1.8V to +5.5V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input
VSS
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT25010, CAT25020, CAT25040
ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years -65C to +150C -0.5 V to +6.5 V
D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40C to 85C, unless otherwise specified. Symbol ICC ISB1 ISB2 IL ILO VIL VIH VOL1 VOH1 VOL2 VOH2 Parameter Supply Current Standby Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC > 2.5V, IOL = 3.0mA VCC > 2.5V, IOH = -1.6mA VCC > 1.8V, IOL = 150A VCC > 1.8V, IOH = -100A VCC - 0.2V VCC - 0.8V 0.2 Test Conditions Read, Write, VCC = 5.0V, fSCK = 10MHz, SO open VIN = GND or VCC , CS = VCC , WP = VCC , VCC = 5V VIN = GND or VCC , CS = VCC , WP = GND, VCC = 5V VIN = GND or VCC CS = VCC , VOUT = GND or VCC -2 -1 -0.5 0.7VCC Min Max 2 2 4 2 1 0.3VCC VCC + 0.5 0.4 Units mA A A A A V V V V V V
PIN CAPACITANCE(3) TA = 25C, f = 1 MHz, VCC = 5V Symbol COUT CIN Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) Max 8 6 Conditions VOUT = 0 V VIN = 0 V Units pF pF
Note: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25C
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CAT25010, CAT25020, CAT25040
A.C. CHARACTERISTICS TA = -40C to +85C, unless otherwise specified.(1) VCC = 1.8V-5.5V SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI(2) tFI(2) tHD tCD tWC(4) tV tHO tDIS tHZ tCS tCSS tCSH tWPS tWPH Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time WP Setup Time WP Hold Time 50 50 50 10 10 0 50 100 15 15 15 10 10 0 10 5 75 0 20 25 Min. 30 30 75 75 DC 5 50 2 2 0 10 5 40 Max. VCC = 2.5V-5.5V Min. 20 20 40 40 DC 10 25 2 2 Max. UNITS ns ns ns ns MHz ns s s ns ns ms ns ns ns ns ns ns ns ns ns
Power-Up Timing(2)(3) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 1 Units ms ms
NOTE: (1) AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: 10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL=50pF (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (4) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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FUNCTIONAL DESCRIPTION
The CAT25010/20/40 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25010/20/40 to interface directly with many of today's popular microcontrollers. The CAT25010/20/40 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed.
PIN DESCRIPTION
SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the CAT25010/20/40. Input data is latched on the rising edge of the serial clock for SPI modes (0, 0 & 1, 1). SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT25010/20/40. During a read cycle, data is shifted out on the falling edge of the serial clock for SPI modes (0,0 & 1,1).
Figure 1. Sychronous Data Timing
VIH tCS
CS
VIL tCSS VIH tCSH
SCK
VIL tSU VIH
tWH tH
tWL
SI
VIL
VALID IN
tRI tFI tV tHO tDIS HI-Z
VOH
SO
VOL
HI-Z
Note: Dashed Line= mode (1, 1) - - - - -
INSTRUCTION SET Instruction WREN WRDI RDSR WRSR READ WRITE Opcode 0000 0110 0000 0100 0000 0101 0000 0001 0000 X011(1) 0000 X010(1) Operation Enable Write Operations Disable Write Operations Read Status Register Write Status Register Read Data from Memory Write Data to Memory
Note: (1) X=0 for CAT25010, CAT25020. X=A8 for CAT25040
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CAT25010, CAT25020, CAT25040
WP: WP Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low all write operations are inhibited. WP held low while CS is low will interrupt a write to the CAT25010/20/40. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. Figure 10 illustrates the WP timing sequence during a write operation. HOLD: HOLD Hold The HOLD pin is used to pause transmission to the CAT25010/20/40 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence.
SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT25010/20/40. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1) . CS Chip Select CS: CS is the Chip select pin. CS low enables the CAT25010/ 20/40 and CS high disables the CAT25010/20/40. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway). A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle.
STATUS REGISTER 7 1 6 1 5 1 4 1 3 BP1 2 BP0 1 WEL 0 RDY
BLOCK PROTECTION BITS Status Register Bits BP1 BP0 0 0 0 1 Array Address Protected None CAT25010: 60-7F CAT25020: C0-FF CAT25040: 180-1FF CAT25010: 40-7F CAT25020: 80-FF CAT25040: 100-1FF CAT25010: 00-7F CAT25020: 00-FF CAT25040: 000-1FF Protection No Protection Quarter Array Protection
1
0
Half Array Protection
1
1
Full Array Protection
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STATUS REGISTER
The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25010/ 20/40 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch. When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected, the user may only read from the protected portion of the array. These bits are non-volatile.
DEVICE OPERATION
Write Enable and Disable The CAT25010/20/40 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. If WP pin is held low, the write enable latch is reset to the write disabe state, regardless of the WREN Instruction. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25010/20/40, followed by the 8-bit address for CAT25010/20/40 (for the 25040, bit 3 of the read data instruction contains address A8). After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing
Figure 2. WREN Instruction Timing
CS
SCK
SI
0
0
0
0
0
1
1
0
SO Note: Dashed Line = mode (1, 1) - - - - -
HIGH IMPEDANCE
Figure 3. WRDI Instruction Timing
CS
SCK
SI
0
0
0
0
0
1
0
0
SO Note: Dashed Line = mode (1, 1) - - - - -
HIGH IMPEDANCE
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CAT25010, CAT25020, CAT25040
to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. Read sequece is illustrated in Figure 4. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Reading status register is illustrated in Figure 5.
WRITE Sequence The CAT25010/20/40 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25010/20/40. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25010/20/40. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the
Figure 4. Read Instruction Timing
CS 0 SCK
OPCODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BYTE ADDRESS 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0
DATA OUT
SI
0
0
0
0
0 X*
SO
HIGH IMPEDANCE
D7 D6 D5 D4 D3 D2 D1 D0
MSB
*Please check the instruction set table for address X=0 for 25010, 25020 ; X=A8 for 25040 Note: Dashed line = mode (1,1)----
Figure 5. RDSR Instruction Timing
CS 0 SCK
OPCODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SI
0
0
0
0
0
1
0
1
DATA OUT
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
Note: Dashed Line= mode (1, 1) - - - - -
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT25010, CAT25020, CAT25040
address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 8-bit address for 25010/20/40 (for the 25040, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction
Page Write The CAT25010/20/40 features page write capability. After the initial byte, the host may continue to write up to 16 bytes of data to the CAT25010/20/40. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only restriction is that the X (X=16 for CAT25010/20/40) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. The CAT25010/20/40 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. Status Register Write To write to the status register, the WRSR instruction should be sent. Only Bit 2 and Bit 3 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register.
Figure 6. Write Instruction Timing
CS 0 SCK
OPCODE
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
21
22
23
BYTE ADDRESS 1 0 A7
DATA IN
SI
0
0
0
0
X* 0
0
A0 D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) - - - - - *X=0 for 25010, 25020 ; X=A8 for 25040
Figure 7. WRSR Timing
CS 0 SCK
OPCODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA IN
SI
0
0
0
0
0
0
0
1
7
MSB
6
5
4
3
2
1
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) - - - - -
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CAT25010, CAT25020, CAT25040
DESIGN CONSIDERATIONS The CAT25010/20/40 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. After power up, CS must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the CAT25010/20/40 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid opcode is received, no data will be shifted into the CAT25010/20/40, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again.
Figure 8. Page Write Instruction Timing
CS
0 SCK
1
2
3
4
5
6
7
8
13
14
15 16-23
24-31
16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
OPCODE
BYTE ADDRESS 0 1 0 A7 A0
Data Byte 1
DATA IN Data Byte 2 Data Byte 3 Data Byte N 0 7..1
SI
0
0
0
0
0 X*
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) - - - - -
*X=0 for 25010, 25020 ; X=A8 for 25040
Figure 9. HOLD Timing
CS tCD SCK tHD HOLD tHZ SO
HIGH IMPEDANCE
tCD
tHD
tLZ
Note: Dashed Line= mode (1, 1) - - - - -
Figure 10. WP Timing
t WPS t WPH
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) - - - - -
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E D
A2
A
A1
L
e b2 b
eB
SYMBOL A A1 A2 b b2 D E E1 e eB L
MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115
NOM
MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150
24C16_8-LEAD_DIP_(300P).eps
0.46
7.87 6.35 2.54 BSC 0.130
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT25010, CAT25020, CAT25040
8-LEAD 150 MIL WIDE SOIC (V)
E1 E
D
h x 45 C A 1
e b
A1 L
SYMBOL A1 A b C D E E1 e h L 1
MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80
NOM
MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 BSC 0.25 0.40 0 0.50 1.27 8
24C16_8-LEAD_SOIC.eps
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT25010, CAT25020, CAT25040
8-LEAD TSSOP (Y)
D
8 5
SEE DETAIL A
c
E
E1
E/2
1
4
GAGE PLANE
PIN #1 IDENT. 1 A2 L 0.25
SEATING PLANE SEE DETAIL A
A
e b
A1
SYMBOL A A1 A2 b c D E E1 e L 1
MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00
NOM
MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00
0.90
3.00 6.4 4.40 0.65 BSC 0.60
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MO-153
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT25010, CAT25020, CAT25040
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
D
A1
A2 A3
D2
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40
b e 3xe E2
PIN 1 ID
L
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
TDFN2X3 (03).eps
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MO-229
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8 LEAD MSOP (Z)
E1
E
e
D A2 GAUGE PLANE
A
b
A1
L
SYMBOL A A1 A2 b D E E1 e L
MIN 0.00 0.75 0.22 2.90 4.80 2.90 0.40 0
NOM
MAX 1.10 0.15 0.95 0.38
3.00 4.90 3.00 0.65 BSC
3.10 5.00 3.10 0.8 8
8-lead_MSOP3.eps
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC Specification MO-187. 3. Stand off height/coplanarity are considered as special characteristics.
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT25010, CAT25020, CAT25040
PACKAGE MARKING
8-Lead PDIP 8-Lead SOIC
25040LI FYYWWC
CSI = Catalyst Semiconductor, Inc. 25040L = Device Code: 25010L 25020L 25040L I = Temperature Range YY = Production Year WW = Production Week C = Product Revision F = Lead Finish 4 = NiPdAu 3 = Matte-Tin
25040VI FYYWWC
CSI = Catalyst Semiconductor, Inc. 25040V = Device Code: 25010V 25020V 25040V I = Temperature Range YY = Production Year WW = Production Week C = Product Revision F = Lead Finish 4 = NiPdAu 3 = Matte-Tin
8-Lead TSSOP
8-Lead MSOP
YMCF 25040
Y M C 25040 = Production Year = Production Month = Product Revision = Device Code: 25010 25020 25040 I = Industrial Temperature Range F = Lead Finish 4 = NiPdAu 3 = Matte-Tin
NNNN YMR
NNNN = Device Code Matte Tin NiPdAu 25010 ABPH ABPJ 25020 ABPF ABKP 25040 ABPG ABCY Y = Production Year M = Production Month C = Production Revision
Notes: (1) The circle on the package marking indicates the location of Pin 1.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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8-Pad TDFN (2x3mm)
XXN NNN YM
XX = Device Code Matte-Tin 25010 FH 25020 FE 25040 FF N = Traceability Code Y = Production Year M = Production Month
NiPdAu FG FC FD
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CAT25010, CAT25020, CAT25040
EXAMPLE OF ORDERING INFORMATION
Prefix CAT Device # 25040 Suffix V I - G T3
Optional Company ID
Product Number 25040: 4K 25020: 2K 25010: 1K(4)
Temperature Range I = Industrial (-40C to + 85C) A = Automotive (-40C to + 125C)(4)
Tape & Reel T: Tape & Reel 3: 3000/Reel
Package L : PDIP V : SOIC, JEDEC Y : TSSOP VP2 : TDFN Z : MSOP(4)
Lead Finish G: NiPdAu Blank: Matte-Tin
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT25040VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For availability, please contact your nearest Catalyst Semiconductor Sales office.
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REVISION HISTORY
Date 10/13/05 12/09/05 Rev. N O Reason Update D.C. Operating Characteristics Update Ordering Information Update Pin Configuration Update D.C. Operating Characteristics Update Pin Impedance Characteristics Update Figure 2, 3, 4, 6, 8 Add Tape and Reel Update Ordering Information Update D.C. Operating Characteristics Update A.C. Characteristics Update Pin Description Update Features Update Description Update A.C. Characteristics Update Package Marking Remove Tape and Reel Update Example of Ordering Information Add TDFN and MSOP packages Update Package Marking Update Ordering Information Update Example of Ordering Information
03/21/06
P
06/30/06
Q
07/31/06
R
10/13/06
S
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Publication #: Revison: Issue date:
1006 S 10/13/06

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